Hardware Lab

Public docs for Hardware Lab — the same topic as in-app User Guide Chapter 23 (23_hardware_lab). Citation-ready definition: What is Hardware Lab?. Product surface: /embedded#hardware-lab. Official desktop commit: cf6b1f7.

This site also has a separate public chapter for OTA Updates at /docs/ota-updates. That OTA chapter is not Hardware Lab.

What this chapter covers

• Virtual hardware-in-the-loop (HIL) on a virtual clock
• Timeline scenarios, assertions, pass/fail
• Where in the app: Tools → Hardware Lab (HIL)...; also Intelligence Panel → Virtual Board → Open Hardware Lab
• Bench — 2D pinout/board views A–E (virtual parts, wires, live mirror; not 3D)
• Run on Device — SSH/Linux may push a temporary hil_device_agent; Arduino USB serial score
• Record — SSH pin watch or USB recorder sketch
• Mirror on the virtual board (default on)
• The 33-board library (Raspberry Pi is in that count)
• CI Hardware Lab GitHub Action and Board Library Manager
• Free/base vs Pro AI (AI Scenario / AI Fix)
• Also in the Oct 9 PC build — local web Composer and editor, and the desktop workbench and Cloud Portal toolbar (not virtual HIL)

What Hardware Lab is

Hardware Lab runs your device code against a simulated board — pins, I2C, UART — on a virtual clock, with timeline scenarios and assertions that return pass/fail in milliseconds. Then Run on Device: SSH/Linux may push a temporary hil_device_agent and diff sim vs bench; Arduino USB serial score (no standing agent; no C++ edge-diff).

Where in the app: Tools → Hardware Lab (HIL)...; also Intelligence Panel → Virtual Board → Open Hardware Lab.

It is not the Fleet Test Panel. Fleet Test Panel is device-connected test suites under Fleet tools. See Fleet Management §Test Panel and the Related note there.

Simulate → assert → Run on Device → diff

1. Simulate — run the file against a virtual board. The simulator uses simulated time, so a sleep() advances the clock instantly. A 30-second hardware scenario can finish in under a millisecond and give the same answer every run. That is a virtual clock, not wall-clock electrical HIL.
2. Assert — put stimuli on a timeline, then state expectations: pin states, pulse counts, I2C writes, log output. You get pass/fail with the check that failed — not a wall of serial output.
3. Run on Device — SSH/Linux may push a temporary hil_device_agent + sim vs bench diff; Arduino USB serial score (no standing agent; no C++ edge-diff). Scenario inputs are GPIO-API injected (not electrical jumpers). Outputs and timing are real on the SSH/Linux road. That helper is temporary for the run.
4. Diff — compare simulation and bench edge by edge: matched edges with timing skew in milliseconds, edges the device never produced, and edges only the device produced.

Record — SSH pin watch or USB recorder sketch; both become replayable stimuli.

Mirror on virtual board (default on) shows live edges on Board View / Bench during a real run.

Bench (A–E)

Bench is a 2D pinout/board view (layouts A–E) — not a 3D CAD scene. Phase F (3D) is not started. Layouts A–E carry virtual parts, wires, and a live mirror of pin state.

A separate 3D world plugin for Hardware Lab and the AI Agent Hierarchy builder is coming to Pro and Teams Pro. It is not purchasable yet and does not replace this free 2D Bench.

33 boards

The library is 33 boards with real pin maps. Raspberry Pi is in that count. Simulation and Generic Linux GPIO are in the 33 as well — not only Jetson, Arduino, and ESP32.

The same board registry feeds Hardware Lab, the Board Library Manager, and the editor's board picker. Pin numbering follows the platform (sketch-style on Arduino; BCM-compatible on Jetson).

Also ships: CI Hardware Lab GitHub Action + Tools → Board Library Manager... (same 33-board registry).

Agents — what Hardware Lab does and does not install

AidaIDE is agentless SSH/SFTP by default. Terminal, SFTP, and LCOT on a normal host need only standard SSH/SFTP.

SSH/Linux Run on Device and Record may push a tiny temporary HIL helper (hil_device_agent) over SSH/SFTP for that run. Arduino USB serial score has no standing agent and no C++ edge-diff. There is no standing Hardware Lab agent.

Free vs Pro

There is no separate Hardware Lab license. See pricing. Optional Pro is $19/mo or $190/yr. Teams Pro is $70/mo or $700/yr for 5 seats.

OS and download

AidaIDE ships for Windows today. macOS and Linux builds are in progress. A Linux experimental source tarball is available to try. Create a free account to download — there is no naked installer path.

Also in the Oct 9 PC build

These notes are from the Oct 9 PC build (7e4239d, 1a26cef, c4f622f, cd9acb2, ca26052). They are not Hardware Lab. The first three are the local web Composer and editor, the browser surfaces of that PC build. The last two are the desktop window.

Native IC and SoC debugger controls

On the browser IC canvas and the browser SoC canvas, Run a saved circuit to attach the native debugger. The Live debug panel is that debugger. Controls are Pause, Resume, Step, Set breakpoint, Clear breakpoint, and Inspect wire, over the existing private owned-worker channel. Pause on start (SignalFlow only). Step advances the next native wave. Inspect wire can report "No packet has been observed on this wire."

Saved SoC wire aliases and browser workspace restore

On the browser SoC canvas, a saved wire alias draws only when a retained placement alias resolves: its unique canonical node and the actual linked IC agree. Ambiguous, shadowed, and unknown targets refuse.

Browser workspace restore: a rendered current-window capture saved two local files, cursor positions, and the unsaved flag. Explicit fresh review reopens the clean file at its saved cursor while preserving the other live draft. There is no automatic SSH contact. This checkpoint does not establish complete desktop parity.

Native editor workspaces and shared-IC impact review

Home and PC editor windows retain multi-file views, cursor and scroll positions, and private unsaved drafts. Saved Workspaces explicitly review file restoration into the source window. The dashboard has a Saved workspaces button.

Opening a shared IC displays the saved SoCs and placement IDs affected by its definition. IC mode shows Shared definition: N placements in M SoCs. Unsynced placements detach parameters only. IC writes, Delete, and saved Undo refuse while an actual owned dependent SoC has not observed cleanup. This is not a new authorization capability.

One-arrangement workbench layouts

On the desktop window, the workbench is either all plain tabs or all Classic. Adopting a connection tab while Classic is active returns every panel to its tab first, with a toast. apply_classic, classic_all, and Classic on connect wait while any connection tab in the main window is unconnected. Classic layout for this connection lays out every connected tab.

The three-pane workspace keeps its proportions. Sidebar and intelligence sashes come from the saved panel sizes, else the first layout's fractions, else 20/20. The layout re-applies once the last part is home.

Cloud Portal toolbar light

On the desktop toolbar, Portal OFF is a plain grey button with a hollow dot. Connecting or reconnecting is amber and shows the try count. Portal ON is a green button with a solid dot. The tooltip follows the state.

A tunnel the launch brought back says so in its tooltip and once in a toast with a Turn off button. Settings > Cloud Portal > Remote Access Keep-Alive reads: "Turn the Cloud Portal back on when AidaIDE starts, if it was on when AidaIDE closed." resume_on_launch defaults on.

Related

• What is Hardware Lab? — citation-ready definition (canonical URL; /hardware-lab redirects here)
• Embedded — product page
• Fleet Management §Test Panel — device-connected tests, not marketing Hardware Lab
• LCOT Panel — Local Chain of Thought is the command library, not HIL
• OTA Updates — fleet firmware rollouts